In general, with semiconductor memory devices such as DRAMs and field memory devices, a number of redundant rows or columns are included in the normal memory, and are provided in order to replace defective (bad) memory cells in the normal memory array or the rows or columns that contain these defective memory cells.
FIG. 4 shows a configuration for a typical redundant circuit. In this memory circuit, the normal memory array 100 composed of memory cells MC arranged in numerous specific columns and rows is equipped with a redundant memory array 102 consisting of, for example, 2 rows of memory cells MC. Of the memory addresses input via the address base 104, the column address Acol is transmitted to the column decoder 106, and the row address Arow is transmitted to the row decoder 108, and also to the fuse decoders 110A and 110B. When a defective memory cell MCe is present, for example, in the second row of the normal memory array 100, the address of the second column is programmed into the fuse decoder 110A. When a defective memory cell is also present in another row of the normal memory array 100, the address of this other row is programmed into the fuse decoder 110B.
When the output row address Arow indicates the second row of the normal array 100, an L level address agreement signal CO- is generated by the fuse decoder 110A. When this agreement signal CO- is generated, the word line WA of the row in the redundant memory array 102 corresponding to the fuse decoder 110A is driven by the driver DRA, and the row decoder 108 is disenabled. The column decoder 106 decodes the column address Acol as usual, and the bit line Bi indicated by the column address Acol is selected.
In this manner, when the address of a row containing defective memory cells MCe in the legitimate memory array 100 (for example, the second row) is indicated, the memory of a special row in the memory array 102 is accessed instead of the row (2nd row) in the legitimate memory array 100 because the fuse decoder (for example 110A) in which the address of this row has been programmed generates an address agreement signal CO-.
FIG. 5 shows a circuit configuration diagram of a conventional fuse decoder. This fuse decoder consists of a timing adjustment circuit 112, a decoding element 114, a precharge p-type MOSFET 116 and an output timing adjustment NAND gate 118.
The decoding part 114 consists of first and second decoding parts 114A and 114B, where both decoding parts 114A and 114B are composed of n-type MOSFETs M0 to M3 and M0- to M3- and numerous fuses (4) F0 to F3 and F0- to F3- corresponding to the bit number (for purposes of explanation, 4 bits) of the respective row address signals Arow. When, for example, a defective memory cell MCe is present on the tenth row of the normal memory array 100, and this 10th row (binary number 1010) is programmed into the decoder, the fuses F1 and F3 of the second and fourth rows are burnt at the first decoding part 114A, and the fuses F0- and F2- of the first and third rows are burnt at the second decoder part 114B that has been complemented.
The operation of this fuse decoder is explained below in reference to FIG. 6. The timing adjustment circuit 112 inputs a row address Arow A0 to A3 and a complemented row address Arow- A0- to A3-, and synchronization occurs with respect to the system clock CK. Special control signals dc0 to dc3, dc0- to dc3-, PC- and 0E are output to each part 114A, 114B, 116 and 118 according to the timing described below.
During the time when the system clock CK is at the L level, the discharge control signals dc0 to dc3 and dc0- to dc3- assume a disenabled or high impedance state corresponding to the first and second decoding parts 114A and 114B, and simultaneous thereto, the precharge control signal PC- reaches the gate terminal of the p-type MOSFET 116, this MOSFET 116 goes on, and a node ND precharges to level H. During this time, an address signal Arow A0-A3 and a complemented row address signal Arow- A0- to A3- are input to the timing control circuit 112.
Next, when the system clock CK is on the H level, with regard to the timing adjustment circuit 112, the p-type MOSFET 116 goes on, and meanwhile, the discharge control signal dc0 to dc3 corresponding to the address signal Arow A0 to A3 reaches the gate terminal of the n-type MOSFETs M0-M3 of the first decoding part 114A, and simultaneously, the discharge control signal dc0- to dc3- corresponding to the complemented address signal Arow- A0- to A3- reaches the gate terminal of the n-type MOSFETs M0- to M3- of the second decoding part 114B.
For example, when the address signal Arow indicates the 9th row, bits A3, A2, A1 and A0 are (1, 0, 0, 1), and thus the bits dc3, dc2, dc1, dc0 of the discharge control signal corresponding to the first decoding part 114A are (1, 0, 0, 1), and the bits de3-, dc2-, dc1-, dc0- of the discharge control signal with respect to the second decoding part 114B are (0, 1, 1, 0). Thus, the first and third of the n-type MOSFETs M0 and M3 go on at the first decoding part 114A, but the fuse F3 alone of the third column is cut, and thus only the fuse F0 of the first column is on. In addition, at the second decoding part 114B, the n-type MOSFETs M1- and M2- of the second and fourth columns go on, but the fuse F2- of the third column is cut, and thus only the fuse F1- of the second column is on. As a result, the voltage (H level) that had been precharged at the node ND discharges by way of the discharge circuit of the fuse F1- and the n-type MOSFET M1- of the second column pertaining to the second decoding part 114B and the discharge circuit of the fuse F0 and the n-type MOSFET M0 of the first column pertaining to the first decoding part 114A, and the node ND assumes the L level. On the other hand, the output enable signal OE reaches the NAND gate 118 from the timing control circuit 112, but at this time, the voltage level of the node ND is at the L level and the output discharge voltage of the NAND gate 118 is at the H level.
However, when the address signal Arow indicates the address (10th row) that is programmed into the fuse decoder, the bits dc3, dc2, dc1, dc0 of the discharge control signal that reaches the first decoding part 114A from the timing control circuit 112 are (1, 0, 1, 0), and the bits dc3-, dc2-, dc1-, dc0- of the discharge control signal that reaches the second decoding part 114B are thus (0, 1, 0, 1). In this case, the n-type MOSFETs M1 and M3 of the 2nd and 4th columns go on at the first decoding part 114A, and the fuses F1 and F3 are both cut. Although the n-type MOSFETs MO- and M2- of the first and third columns go on at the second decoding part 114B, both of the fuses F0- and F2- are cut. Consequently, the node ND does not discharge, and the H level voltage obtained in the precharge is maintained. As a result, when the output enable signal OE reaches the NAND gate 118, the L level voltage signal produced by inversion of the voltage level (H level) of the node ND is generated as an address agreement signal CO- from the output terminal of the NAND gate 118.
As described above, in the first half of the system clock cycle with conventional fuse decoders, the node ND is precharged to the H level, and then in the second half of the system clock cycle, the address signal Arow and the complemented address signal Arow- that are input to the first and second decoding parts 114A and 114B are read or identified, and the node ND is selectively discharged depending on the results of the read, whereupon an address agreement signal CO- is generated when no discharge occurs at the node ND. In this manner, because the period when the node is precharged is set in each system clock cycle, timing adjustment for each part of the decoder is difficult when the period of the address signal or the period of the memory access is short. In addition, when the value of the input address signal is near that of the set address, for example, when they differ only by one, the node must be discharged with just one of the fuses, which causes problems in terms of the reliability of the discharge circuit. In addition, the voltage level of the node ND changes depending on fluctuations in the discharge characteristics or precharge characteristics, and there is the danger that erroneous discharge signals might be output from the AND gate 118.
In addition, with the aforementioned conventional fuse decoders, not only is there a decoding section 114A for the address signal Arow, but there is also a decoding part 114B for the complemented address signal Arow-, and thus two times the number of fuses F0 to F3 and F0- to F3- are present relative to the bit number of the address signal. Coding relative to the complemented address signal Arow- is carried out because the bit information of the input address signal cannot be confirmed at the columns where the fuses have been cut. For example, at the second and fourth columns of the first decoding part 114A, the fuses F1 and F3 are cut, and thus it does not matter whether the n-type MOSFETs M1 and M3 are on or off. A discharge circuit is not formed, and thus the bit information (0 or 1) of the first and fourth columns of the input address signal Arow cannot be identified. Rather, in the second decoder part 114B where the logic of the first decoder part 114A is inverted, the first and fourth column fuses F0- and F3- are not cut, and thus the first and fourth column bit information (0 or 1) of the complemented address signal Arow- can be identified.
Although functional assurance is provided in this manner, the establishment of a double set of deciding parts or fuses is a significant disadvantage in terms of reliability and integration. If the bit number of the discharge control and address signals increases by a factor of two, the wiring width also increases by a factor of two which decreases the level of integration. In addition, the fuses are generally physically burnt using a laser, and there is a yield with this process as well. Thus, the yield decreases as the number of fuses increases. In addition, the surface area taken by the fuses is large, and the surface area of the redundant circuit increases as the number of fuses increases, which causes problems with chip surface area.
In addition, as described above, the action of each part is finely timed, and thus the reliability of the timing adjustment circuit 112 not only greatly affects the reliability of the decoder, but also takes a corresponding circuit surface area in the decoder.
In addition, for example, with field memories, when a memory access is carried out a synchronously between the read side and the write side, the decoding operation can function only with respect to a single input address at a time in the aforementioned conventional fuse decoders, and thus the respective fuse decoders of the read and write side must be ready.